This application claims the benefit of Korean patent application No. 98-10687, filed Mar. 27, 1998, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) source driver with increased current driving capacity for driving the LCD and converting digital video signals into positive and negative analog video signals for a dot inversion method.
2. Discussion of the Related Art
Video signals that do not have a constant polarity, but are inverted alternately, are supplied to an LCD because the expected life span of each liquid crystal cell of the LCD is shortened by a constant application of the video signals having a fixed polarity.
A source driver converts digital video signals into negative and positive polarity digital video signals, which are lower and higher in voltage, respectively, than the common voltage Vcom. The source driver converts the digital video signals to analog video signals of higher current driving capacity, and supplies each liquid crystal cell with the analog video signals. In general, the common voltage Vcom has a set point of 5V, the positive polarity video signals have a voltage range of 5 to 10V, and the negative polarity video signals have a voltage range of 0 to 5V.
There are several inversion methods, such as a line inversion method, a column inversion method and a dot inversion method, for driving an LCD panel with an LCD source driver. In the line inversion method, an LCD having a matrix-structured cell array is inverted alternately by row, and the polarities of the video signals applied to each odd and even rows are inverted alternately. In the column inversion method, where the LCD is inverted by column, and the polarities of the video signals applied to each odd and even columns of the LCD are alternately inverted.
However, flicker may occur in an LCD using the line or column inversion method when two adjacent rows or columns are alternately inverted. Thus, the dot inversion method, which mixes the line inversion method with the column inversion method, is used.
FIG. 1 shows polarities of video signals supplied to each cell of LCD driven by the dot inversion method. Referring to FIG. 1, flicker can be greatly reduced by having the polarities of the LCD cells differ from one another both vertically and horizontally. The dot inversion method, which applies mainly to high quality image displays in the LCDs, is becoming more prevalent in fields such as TV""s, computer monitors, and the like.
FIG. 2 is a block diagram of an LCD source driver according to the related art, which shows the components necessary for driving only one channel. Referring to FIG. 2, 4 bits of digital video signals 40 to 43, and a polarity control signal 44, which controls the polarities of the digital video signals 40 to 43, are inputted. The digital video signals having voltage levels of Vss to Vdd are converted to the positive polarity analog video signals of Vss1 to Vdd1 through a positive polarity video signal generating path 48 formed by a level shifter 46, a D/A converter 54 and a sample and hold circuit 56.
The digital video signals having voltage levels Vss to Vdd are converted to the negative polarity analog video signals of Vss1 to Vdd1 range through a negative polarity video signal generating path 52 formed by another level shifter 50, another D/A converter 68 and another sample and hold circuit 70. The converted positive and negative analog video signals are inputted to an output buffer 64.
The polarity control signal 44 is converted to output control signals 30 and 34 controlling the output operation of the output buffer 64 through a pair of level shifters 28 and 32, and then the output control signals 30, 34 are applied to the output buffer 64. The output buffer 64 (a type of multiplexer) selects either the negative or positive polarity video signal, which is inputted through the positive polarity video signal generating path 48 and the negative polarity video signal generating path 52, by the output control signals 30 and 34, which control the output buffer 64 according to the polarities of the video signals supplied to the LCD cells.
The positive or negative polarity analog video signal outputted from the output buffer 64 drives a channel of an LCD. Namely, two video signal generating paths of the negative and positive polarity are required to drive a single channel, which causes an increase in a layout area of a chip due to an increased number of elements of the driver circuit.
FIG. 3 shows a circuit of an output buffer of an LCD source driver according to the related art. The positive polarity video signals are transferred to an output terminal 66 through two PMOS transistors Q1 and Q2 connected in series. A gate of the PMOS transistor Q1 is controlled by the output control signal 30. The negative polarity video signals are transferred to the output terminal 66 through two NMOS transistors Q3 and Q4 connected in series. The PMOS transistor Q2 and the NMOS transistor Q4 protect the PMOS transistor Q1 and the NMOS transistor Q3 from the high voltage Vdd2 and the low voltage Vss at the output terminal.
However, a maximum voltage level Vdd1 of the positive polarity video signals or a minimum voltage level Vss2 of the negative polarity video signals is applied between sources and drains of the protecting devices of the PMOS transistor Q2 and the NMOS transistor Q4 at the moment that the positive and negative polarity video signal are outputted alternately from the output buffer 64. Such a high voltage applied instantly to the protecting devices decreases the life spans of the protecting devices.
Accordingly, the present invention is directed to an LCD source driver that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an LCD source driver with a reduced number of components.
Another object of the present invention is to provide an LCD source driver which prevents protecting devices in an output terminal of an output buffer from receiving high voltage instantaneously due to a voltage difference between the negative polarity video signal and a positive polarity video signal.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in accordance with one aspect of the present invention there is provided an LCD source driver having a plurality of driving channels including a control logic responsive to an internal polarity control signal, a first clock signal and a second clock signal, the control logic being inputted alternately and consecutively with digital video signals of multiple bits including odd channel digital video signals and even channel digital video signals, the control logic generating the odd channel digital video signals and the even channel digital video signals corresponding to a logic value of the internal polarity control signal in one of an inputted order and a reversed order, a shift register being activated successively and outputting a plurality of enabling signals, a latch block having a plurality of latches for receiving the odd channel digital video signals and the even channel digital video signals synchronized by the plurality of enabling signals, the latch block generating simultaneously the odd channel digital video signals and the even channel digital video signals when the enabling signals are activated, a negative polarity video signal processor for converting the odd channel digital video signals outputted from the latch block into negative polarity analog video signals having a voltage lower than a common voltage and increased current driving capacity, a positive polarity video signal processor for converting the even channel digital video signals outputted from the latch block into positive polarity analog video signals having a voltage higher than the common voltage and having a higher current driving capacity, and a switching block having a plurality of switching circuits for receiving the negative polarity analog video signals and the positive polarity analog video signals, wherein odd switching circuits of the switching block generate the positive polarity analog video signals on HIGH of the internal polarity control signal and the negative polarity analog video signals on LOW of the internal polarity control signal, and wherein even switching circuits of the switching block generate the negative polarity analog video signals on HIGH of the internal polarity control signal and the positive polarity analog video signals on LOW of the internal polarity control signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.